Beta engineering and circuit styles for SEU hardening PD-SOI SRAM cells

摘要

SOI technologies have long been used for SEU-hardened SRAMs and other radiation-hard circuits. However, to maintain their advantages in the submicron regime, it is essential that the strength of the floating body effects (FBE) and the role of the parasitic bipolar transistor (PBJT) should be minimized. In this work these are achieved by reducing the gain β of the PBJT by controlling the carrier recombination lifetime of the SOI film. Two sets of devices (A and B) were fabricated on 0.35 μm PD SOI technology, where Device A underwent a lifetime "killing"-processing step to control the single event upset (SEU) vulnerability. These devices were experimentally characterized and simulated and the results verified the benefits' of lifetime "killing". Additional SEU control was achieved by optimizing the circuit design of the cell through the incorporation of suitable delay elements.