INTEGRATION ISSUES WITH HIGH k GATE STACKS

摘要

Several of the key problems associated with the integration of high k gate staeks (dielectrics plus gate electrodes) in a gate first process are described, starting with the basic material selection. Thermal compatibility of the group Ⅲ and Ⅳ dielectrics with conventional junction formation temperatures requires techniques such as nitridation or alloying with SiO_2 or Al_2O_3. If performed properly these processes minimize the equivalent oxide thickness (EOT) and can also reduce gate leakage and boron penetration from the gate electrode. Pre-metal annealing at elevated temperature, e.g., 600℃, and post-metal annealing in deuterium provide significant enhancements in channel mobility and device stability during stressing. Although not all the criteria for success can be simultaneously met, these more-optimized processes result in improved devices, including those whose channel mobilities at 1 nm EOT are within 90% of that of pure oxide and those which are projected to be stable for over 10 years of operation.