Characterization, integration and reliability of HfO$_2$ and LaLuO$_3$ high-κ/metal gate stacks for CMOS applications

摘要

The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-kappa/metal gate stacks. LaLuO3 and HfO2 are investigated as two different high-kappa oxides on silicon in conjunction with TiN as the metal electrode. LaLuO3 and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO3 is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO3 on germanium, germanate formation is shown. LaLuO3 is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70µA/µm at 1µm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO3 in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-kappa oxide. Different approaches are presented for a further EOT reduction with LaLuO3 and HfO2. Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO2 gate stacks is scalable below 1 nm by the use of thinned interfacial SiO2. The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the gate electrode to decrease the EOT of HfO2 gate stacks. A lower limit found was EOT=5 Å for Al doping inside TiN. The doping of TiN on LaLuO3 is proven by electron energy loss spectroscopy (EELS) studies to modify the interfacial silicate layer to La-rich silicates or even reduce the layer. The oxide quality in Si/HfO2/TiN gate stacks is characterized by charge pumping and carrier mobility measurements on 3d MOSFETs a.k.a. FinFETs. The oxide quality in terms of the number of interface (and oxide) traps on top- and sidewall of FinFETs is compared for three different annealing processes. A high temperature anneal of HfO2 improves significantly the oxide quality and mobility. The gate oxide integrity (GOI) of gate stacks below 1 nm EOT is determined by time-dependent dielectric breakdown (TDDB) measurements on FinFETs with HfO2/TiN gate stacks. A successful EOT scaling has always to consider the oxide quality and resulting reliability. Degraded oxide quality leads to mobility degradation and earlier soft-breakdown, i.e. leakage current increase.