首页> 外文会议>Design-Process-Technology Co-optimization for Manufacturability X >Design Technology Co-optimization for 14/10nm Metal1 Double Patterning Layer
【24h】

Design Technology Co-optimization for 14/10nm Metal1 Double Patterning Layer

机译:14 / 10nm Metal1双图案层的设计技术共同优化

获取原文
获取原文并翻译 | 示例

摘要

Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metall layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metall layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.
机译:设计和技术协同优化(DTCO)可以满足设计需求,生成可靠的设计规则,并在设计初期避免使用不友好的图案,以确保通过当前工艺的技术能力实现高水平的产品可制造性。本文的DTCO方法主要包括设计规则转换,布局分析,模型验证,热点分类和设计规则优化。 DTCO与双图案(DPT)的相关性可以优化相关的设计规则并生成更友好的布局,从而满足14 / 10nm技术节点的要求。该实验演示了DPT兼容DTCO的方法,该方法已从14 / 10nm节点应用于金属层。我们工作中建议的DTCO工作流程是优化14/10 nm技术节点Metall层设计规则的有效解决方案。并且,本文还讨论并验证了如何调整可感知DPT的金属层中U形和L形结构的设计规则。

著录项

  • 来源
  • 会议地点 San Jose CA(US)
  • 作者单位

    Key Laboratory of Microelectronics Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;

    Key Laboratory of Microelectronics Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;

    Key Laboratory of Microelectronics Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;

    Key Laboratory of Microelectronics Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;

    Mentor Graphics (Shanghai) Electronic Technology Co, Ltd, 5F Building 2, No.759 South Yang Gao Road. Pudong New District, Shanghai, 200127, China;

    Mentor Graphics (Shanghai) Electronic Technology Co, Ltd, 5F Building 2, No.759 South Yang Gao Road. Pudong New District, Shanghai, 200127, China;

    Mentor Graphics (Shanghai) Electronic Technology Co, Ltd, 5F Building 2, No.759 South Yang Gao Road. Pudong New District, Shanghai, 200127, China;

    Key Laboratory of Microelectronics Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    DTCO; double patterning; Design rule optimization; IC manufacture; Lithography technology;

    机译:DTCO;双重图案设计规则优化; IC制造;光刻技术;

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号