Stitch-less Double Patterning Technology for Reduced Wire Length Three-layer Routing Solution

摘要

Here we proposed lithography based layer decomposition for reduced wire length three-layer routing solution using Double Patterning Technology (DPT). First we proposed a routing algorithm of three-layer (HVH) restricted dogleg routing solution to minimize the wire length of the chip to be designed. Next we designed a layer decomposition algorithm of the obtained routing solution using DPT to increase the quality of printability on wafer. Finally, we showed that the proposed DPT based layer decomposition is stitch-less and it reduces overlay errors and line-end effects. This is the most acceptable solution using current lithography process for 32-nm node and beyond.