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Methods for pattern matching in a double patterning technology-compliant physical design flow
Methods for pattern matching in a double patterning technology-compliant physical design flow
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机译:符合双重图案技术的物理设计流程中的图案匹配方法
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摘要
A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.
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