A 1.2V Sample-and-Hold Circuit for 14-Bit 250MS/s Pipeline ADC in 65nm CMOS

摘要

This paper presents a design of a high speed, high accuracy, low voltage sample and hold circuit used in pipeline analog to digital converter for wireless communication applications in 65nm CMOS technology. Due to the low intrinsic gain of 65nm process, an OTA with simplified class A/B output stage and gain-boosting technique is introduced in the circuit, acquiring a gain of more than 80dB, so as to achieve a 14-bit linearity and a rail-to-rail output swing as well with low power consumption. The linearity issue of the switches is also taken into consideration. The simulation result shows a maximum SFDR of 96.3dB at 11MHz, 95.0dB at 149MHz and 87.1dB at 405MHz input frequency under a sampling rate of 250MS/s.