A high-performance sample-and-hold circuit for 14-bit 125MS/s pipelined ADC

摘要

This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches'' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18µ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s and preserves 91dB SFDR and 82dB SNDR with the input frequency up to 160MHz. The designed circuit has been used in the front end of 14-bit 125MS/s pipelined ADC adapted for single-ended applications.