A Read-Write Aware Replacement Policy for Phase Change Memory

摘要

Scaling DRAM will be increasingly di.cult due to power and cost constraint. Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-e.ective and power-e.cient manner. However, PCM incurs relatively long latency , high write energy, and .nite endurance. To make PCM an alternative for scalable main memory, write tra.c to PCM should be reduced, where memory replacement policy could play a vital role. In this paper, we propose a Read-Write Aware policy (RWA) to reduce write tra.c without performance degradation. RWA explores the asymmetry of read and write costs of PCM, and prevents dirty data lines from frequent evictions. Simulations results on an 8-core CMP show that for memory organization with and without DRAM bu.er, RWA can achieve 33.1% and 14.2% reduction in write tra.c to PCM respectively. In addition, an Improved RWA (I-RWA) is proposed that takes into consideration the write access pattern and can further improve memory e.ciency. For organization with DRAM bu.er, I-RWA provides a signi.cant 42.8% reduction in write tra.c. Furthermore, both RWA and I-RWA incurs no hardware overhead and can be easily integrated into existing hardware.