首页> 外文会议>33rd European Solid-State Device Research Conference (ESSDERC 2003); Sep 16-18, 2003; Estoril, Portugal >Analysis of Laterally Asymmetric Channel Design in Fully Depleted Double Gate (DG) SOI MOSFETs for High Performance Analog Applications
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Analysis of Laterally Asymmetric Channel Design in Fully Depleted Double Gate (DG) SOI MOSFETs for High Performance Analog Applications

机译:用于高性能模拟应用的全耗尽双栅(DG)SOI MOSFET的横向非对称沟道设计分析

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摘要

Based on analytical modeling, 2D simulation and experimental results, the work demonstrates the potential benefits of using laterally asymmetric channel design over uniform doping in DG SOI MOSFETs for achieving excellent analog performance. We show that the asymmetric channel design in DG MOSFETs makes it possible to achieve a DC gain of 80 dB, an Early voltage of over 1200 V and nearly ideal values (~38 V~(-1)) of transconductance-to-current ratio for L_(eff)=1.64μm well in excess of those reported so far. Analysis shows new opportunities for realising future high performance analog circuits with GC DG MOSFETs.
机译:基于分析模型,二维仿真和实验结果,这项工作证明了使用横向非对称沟道设计优于DG SOI MOSFET中的均匀掺杂来实现出色的模拟性能的潜在好处。我们证明了DG MOSFET的非对称沟道设计可以实现80 dB的直流增益,超过1200 V的早期电压以及跨导电流比的接近理想值(〜38 V〜(-1)) L_(eff)=1.64μm,远远超过迄今为止报道的值。分析显示了使用GC DG MOSFET实现未来高性能模拟电路的新机会。

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