A Study of Pattern Density and Process Variations Impact on the Reliability Performance of Multi-Level Capacitance Structure in Low-k Copper Interconnects

摘要

Multi-level Metal-Oxide-Metal Capacitors (MOM) is widely utilized in CMOS process. It is an inter-digitated three dimensional multi-level finger capacitor structure formed in dual damascene copper metal layers in the Back-end-of-Line (BEOL) process. Key factors impacting the Time-dependent dielectric breakdown (TDDB) performance of MOM are identified, and results are discussed in this paper. Voltage Ramp (VRamp) analysis is used as the response of the performance of TDDB as it is well known that they are correlated to electric field acceleration parameter of the SQRT E model.