3D embedded wafer-level packaging technology development for smart card SIP application

摘要

Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production[1–3]. Known good dies are rebuilt in a molding compound matrix wafer and fan out redistribution layer and bumps are subsequently built on top of the as-formed strata. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture.