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Semiconductor integrated circuits, timing controllers, and display devices

机译:半导体集成电路,定时控制器和显示设备

摘要

PROBLEM TO BE SOLVED: To detect abnormalities in differential transmission lines.SOLUTION: A semiconductor integrated circuit 100 is connected with another circuit via differential transmission lines of N channels CH1 to CHN. Each of N differential transmitters 10 drives the differential transmission line 3 of the corresponding channel via a corresponding differential output pin OUTP/OUTN. An abnormality detection circuit 20 detects abnormalities generated in the differential transmission lines 3 of the N channels. Each of N amplifiers AMP1 detects a potential difference of the differential transmission line 3 of the corresponding channel. Each of N first comparators CMP1 compares an output voltage Vof the corresponding amplifier AMP1 with a predetermined first threshold voltage V. A logic circuit 24 detects abnormalities of a first mode in the differential transmission line 3 of the corresponding channel on the basis of an output of each of the N first comparators CMP1.SELECTED DRAWING: Figure 3
机译:要解决的问题:以检测差分传输线的异常。:半导体集成电路100通过N通道CH1的差分传输线与另一电路连接到CHN。每个N个差分发射器10经由相应的差分输出引脚OUTP / OUTN驱动相应信道的差分传输线3。异常检测电路20检​​测在N个通道的差分传输线3中产生的异常。 N个放大器中的每一个AMP1检测相应通道的差分传输线3的电位差。 n第一比较器CMP1中的每一个将相应的放大器AMP1的输出电压Vof与预定的第一阈值电压V进行比较。逻辑电路24基于输出检测相应通道的差分传输线3中的第一模式的异常N个第一比较器中的每一个CMP1。选择图:图3

著录项

  • 公开/公告号JP6889997B2

    专利类型

  • 公开/公告日2021-06-18

    原文格式PDF

  • 申请/专利权人 ローム株式会社;

    申请/专利号JP20160196718

  • 发明设计人 志水 孝至;

    申请日2016-10-04

  • 分类号H04L25/02;G01R31/08;G01R31/28;

  • 国家 JP

  • 入库时间 2024-06-14 21:43:13

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