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Improvements in or relating to a control circuit employing semi-conductor devices

机译:使用半导体器件的控制电路或与之有关的改进

摘要

826,555. Circuits employing bi-stable magnetic elements. SPERRY RAND CORPORATION. Jan. 25, 1957, No. 2840/57. Class 40 (9). [Also in Group XL (c)] In a circuit comprising a saturable core T2 biased by current in a winding 50 to a saturated state, a further winding 46 is connected to a series of semi-conductors 40, 41 and 42, current due to charge carrier storage set up by input signals at terminals 52, 53 or 54 being supplied through the semi-conductors to drive the core into an unsaturated region. A square clock pulse waveform A is applied over terminal 47 and isolating diodes 43, 44 and 45 to the diodes 40, 41 and 42. During the negative-going waveform diode 43 is reversely biased and no current flows in winding 46, and in the succeeding positive-going wave a small current passes through the back resistance of diode 40 to cause a small current in the winding but since this is insufficient to drive the core from its saturated state, no output appears across the winding 48. If, during the next negative-going clock pulse an input pulse is applied to the junction of diodes 40, 43 forward current flows in diode 40, driving the core further into the saturated region. When the input pulse ceases and the clock pulse reverses, considerable current flows in the reverse sense of diode 40 driving the core from one saturated condition to the other, Fig. 3 (not shown), to produce an output pulse on winding 48. This output pulse is terminated by the next negative-going clock pulse which allows the bias source to restore the core to its original condition. The input signal may be applied over a transformer, Fig. 1 (not shown), and blocking pulses applied to the secondary to prevent reaction on the input due to clock pulses. The circuit may be regarded as an OR gate since when any one of the diodes 40, 41 and 42 is rendered conducting an output appears on winding 48. A winding 55 is biased from a battery 56 so that the output is at battery potential except in the case when an output appears across winding 55. In this manner the circuit may be regarded as an AND gate since only in the absence of any input does the output correspond to the battery 56. The circuit may be arranged so that more than one rectifier 40 must be energized before an output occurs. Specification 826,556, [Group XL (c)], is referred to.
机译:826,555。采用双稳态磁性元件的电路。斯普瑞兰德公司。 1957年1月25日,编号2840/57。 40级(9)。 [也在XL(c)组中]在包括通过绕组50中的电流偏置到饱和状态的可饱和铁心T2的电路中,另一绕组46连接到一系列半导体40、41和42,通过半导体提供的端子52、53或54上的输​​入信号,将铁心驱动到不饱和区域,从而建立电荷载流子存储。方波脉冲波形A施加在端子47上,并在二极管40、41和42上隔离二极管43、44和45。在负向波形期间,二极管43反向偏置,绕组46和绕组46中没有电流流过。在随后的正向波中,小电流流过二极管40的反向电阻,从而在绕组中产生小电流,但是由于这不足以将铁心从饱和状态驱动,因此绕组48上不会出现输出。下一个负向时钟脉冲,一个输入脉冲被施加到二极管40的结点,正向电流在二极管40中流动,驱动磁芯进一步进入饱和区。当输入脉冲停止并且时钟脉冲反向时,大量电流沿二极管40的反向流动,从而将铁心从一种饱和状态驱动到另一种饱和状态(图3(未显示)),从而在绕组48上产生输出脉冲。输出脉冲由下一个负时钟脉冲终止,该时钟脉冲允许偏置源将磁芯恢复到原始状态。该输入信号可以施加在图1的变压器(未示出)上,并且阻塞脉冲施加到次级,以防止由于时钟脉冲而对输入产生反应。该电路可以被视为“或”门,因为当使二极管40、41和42中的任何一个导通时,绕组48上就会出现输出。绕组55从电池56偏置,因此输出处于电池电位,除了在绕组55上出现输出的情况。以这种方式,该电路可以被视为与门,因为只有在没有任何输入的情况下,该输出才对应于电池56。输出发生之前,必须给40通电。请参考规格826,556 [XL(c)组]。

著录项

  • 公开/公告号GB826555A

    专利类型

  • 公开/公告日1960-01-13

    原文格式PDF

  • 申请/专利权人 SPERRY RAND CORPORATION;

    申请/专利号GB19570002840

  • 发明设计人 JR. JOHN CLARK SIMS;

    申请日1957-01-25

  • 分类号H03K3/33;

  • 国家 GB

  • 入库时间 2022-08-23 19:06:04

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