ABSTRACT OF THE DISCLOSUREA frequency synthesized receiver utilizes, as alocal oscillator, a phase-locked loop circuit formed of areference signal oscillator, a voltage controlled oscillator,a programmable divider, a phase comparator, and a low-passfilter. For tuning to a desired frequency, the dividingratio of the programmable divider is controlled by an up/down counter connected in parallel with a shift register.The latter is supplied with a clock pulse signal and abinary coded selecting signal furnished from a micro com-puter. The selecting signal corresponds to a desiredbroadcast frequency. The up/down counter is caused bythe micro computer to count up or down from the countvalue stored in the shift register, thereby causing thereceived frequency to rapidly sweep, at predetermined stepsof, for example, 100 KHz.-1-
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