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A novel three-phase software phase-locked loop based on frequency-locked loop and initial phase angle detection phase-locked loop

机译:基于锁频环和初始相角检测锁相环的新型三相软件锁相环

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This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune to phase jumps and voltage sharp changes. A frequency adaptive digital filter (FADF) is included in FLL to reject harmonics. The FADF uses two strategies to sweep away disturbing signals in a synchronous reference domain. Firstly, specific order harmonics are eliminated by multistage application of delayed signal cancellation (DSC) using estimated delayed signals. Excellent steady-state performance of multistage DSC to reject harmonics is achieved with the help of FLL and interpolation strategy. Secondly, a conventional low-pass (LP) filter damps the rest higher frequency harmonics and noises. Initial phase angle detection PLL could have a high cutoff frequency due to good performance of FADF. Simulations prove the new SPLL responds fast and has precise steady-state output.
机译:本文提出了一种新型的三相软件锁相环(SPLL),它可以在不平衡,污染和频率偏离的情况下快速而准确地运行。这个新提出的SPLL由锁频环(FLL)和初始相位角检测PLL组成。 FLL采用差分算法来检测可能不受相位跳变和电压急剧变化影响的频率误差。频率自适应数字滤波器(FADF)包含在FLL中以抑制谐波。 FADF使用两种策略来清除同步参考域中的干扰信号。首先,通过使用估计的延迟信号通过多级应用延迟信号消除(DSC)消除特定阶次谐波。借助FLL和插值策略,可以实现出色的多级DSC稳态性能,以抑制谐波。其次,传统的低通(LP)滤波器会衰减其余的更高频率的谐波和噪声。由于FADF的良好性能,初始相位角检测PLL可能具有较高的截止频率。仿真证明,新的SPLL响应速度快,并具有精确的稳态输出。

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