Lateral PNP transistor using a latch voltage of NPN transistor

摘要

A lateral PNP transistor having either of the collector or the emitter diffusion layers layered with an n.sup.+ type diffusion layer, is shown. The added layer serves to increase the static electricity withstand stress along a transistor discharging path. A low withstand stress contributes to transistor damage at high breakdown voltages. When an n. sup.+ diffusion layer is formed within a diffusion layer in a lateral PNP transistor the transistor behaves as a combination of two transistors, PNP and NPN, selectively configured.