首页> 外国专利> Transistor arrangement for e.g. MOSFet

Transistor arrangement for e.g. MOSFet

机译:例如的晶体管布置商务部

摘要

The transistor arrangement includes an insulating film, a gate (20) and a source/drain (24) which are all arranged on a semiconductor substrate (11). The gate overlaps the source/drain at its edges. The source/drain are arranged below the gate. In one embodiment the gate is arranged so that it is spaced from the source/drain at its edges by a conducting film spacing part which is in contact with the source/drain. The conducting film spacing part is insulated from the semiconductor substrate and has a conducting film on one of its side walls.
机译:该晶体管装置包括均布置在半导体衬底(11)上的绝缘膜,栅极(20)和源极/漏极(24)。栅极在其边缘与源极/漏极重叠。源极/漏极布置在栅极下方。在一个实施例中,栅极被布置为使得其在其边缘处通过与源极/漏极接触的导电膜间隔部分与源极/漏极间隔开。导电膜间隔部与半导体基板绝缘,并且在其侧壁之一上具有导电膜。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号