PURPOSE:To reduce the memory capacity of a computer and to improve its processing speed by constituting a signal arithmetic value processing phase in hardware and processing it in parallel by a logical element parallel simulation device connected to a universal computer. CONSTITUTION:The universal computer 18 detects the input signal value variation of every corresponding terminal while referring to circuit connection information according to input signal variation information from an external input signal file 23, and stores it in the input/output buffer 17 of the logical element parallel simulation device 11 connected to the computer 18 through a table 21. Plural arithmetic processors 14, gate memory 12, signal value memory 13, etc., which construct the signal arithmetic value processing phase in hardward process the basic element attribute information on a logical model circuit, input/output signal variation information, etc., in parallel on the basis of the storage contents of the buffer 17. Thus, the memory capacity of the computer is reduced and its processing speed is improved.
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