Improved Wells-Tree Adder, Structure, and Method for High-Speed Binary Multipliers

摘要

The present invention relates to a rounding-preserving adder having a reduced number of full adder stages for use in a binary multiplier, wherein the rounding-preserving adder of the present invention sums binary rows of data and stores a plurality of 1-bit (30) bits. And 2-bit 60 full adders. 1-bit 30 and 2-bit 60 full adders add a number of interconnected improved welles-trees that sum binary data from one or more rows to produce a subtotal 74 and a round-up number 76. Arranged with an adder. Each improved well-tree adder has a plurality of stages 70, 110, 130, 150 that include 1-bit 30 and 2-bit 60 full adders that reduce the number of multiple binary data bits, where the final stage ( 36,122,142,162. Multiple conductors interconnect the stages of each improved well-tree adder with the stages in the same well-tree adder and the stages in another improved well-tree adder.