首页> 外国专利> COPLANARITY CORRECTING METHOD AND DEVICE OF SEALED SEMICONDUCTOR DEVICE LEAD

COPLANARITY CORRECTING METHOD AND DEVICE OF SEALED SEMICONDUCTOR DEVICE LEAD

机译:密封半导体器件引线的共面校正方法和器件

摘要

PROBLEM TO BE SOLVED: To enable the coplanarity correction of sealed semiconductor device to be performed stably regardless of the dispersion in the lead length of a sealed semiconductor device. ;SOLUTION: Within the method, the coplanarity of lead 9a is corrected by a method wherein a sealed semiconductor device 9 having the lead 9a externally extended from the side of a sealed body is mounted on a pedestal 8 so that the surface side of the device 9 may be clamped to make a pair of coplamarity corrected bodies 11, 12 with the lead 9a oppositely arranged alternately weld with each other. In such a constitution, the sealed semiconductor device 9 is mounted on the pedestal 8 with a backlash from the inner peripheral surface of the guide wall 8a in the outer periphery of the pedestal 9 as well as said device 9 is clapped with a backlash from the inner peripheral surface of the guide wall 10a in the outer periphery of the clamp 10.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:不管密封半导体器件的引线长度的分散如何,都能稳定地进行密封半导体器件的共面校正。 ;解决方案:在该方法中,通过一种方法校正引线9a的共面性,在该方法中,将具有从密封体一侧向外延伸的引线9a的密封半导体器件9安装在基座8上,从而使器件的表面侧可以将图9中所示的导线9a夹紧,以制成一对经同度校正的主体11、12,其中相对布置的引线9a彼此交替地焊接。在这种结构中,密封的半导体器件9以在基座9的外周中从引导壁8a的内周表面有间隙的方式被安装在基座8上,并且所述器件9被从壳体9的间隙中被反弹地鼓掌。夹具10的外周中的导向壁10a的内周面。版权所有:(C)1997,日本特许厅

著录项

  • 公开/公告号JPH09232492A

    专利类型

  • 公开/公告日1997-09-05

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19960033256

  • 发明设计人 ONODA HAJIME;SATO TAMOTSU;

    申请日1996-02-21

  • 分类号H01L23/50;

  • 国家 JP

  • 入库时间 2022-08-22 03:34:05

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