ADDER CIRCUIT AND LAYOUT STRUCTURE THEREFOR

摘要

PROBLEM TO BE SOLVED: To prepare a block carry generation logic and a block carry propagation logic at an adder circuit to reduce a layout area and to enable high-speed operation. ;SOLUTION: The block carry generation logic over three continuos digits is prepared by G0=g2+p2.g1+p2.p1.g0 and /G0=/p2+/g2./p1+/g2./g1./g0 ('/' shows the inverse of logic). Namely, this /G0 is prepared by a serial circuit 3 serially connecting one P type MOS transistor 106 and two P type MOS transistors 104 and 105 and a serial circuit 4 serially connecting three P type MOS transistor 101, 102 and 103. Besides, this G0 is prepared by a serial circuit 6 serially connecting one N type MOS transistor 107 and two N type MOS transistors 108 and 109 and a serial circuit 7 serially connecting three N type MOS transistors 110, 111 and 112.;COPYRIGHT: (C)1998,JPO