ADDER CIRCUIT AND ASSOCIATED LAYOUT STRUCTURE

摘要

The present invention is to create a block digit rounding generation logic and a block digit rounding propagation logic in the addition circuit so that the layout area can be small and high-speed operation, the block digit rounding generation logic that spans three consecutive digits is represented by the following equation,;G0 = g2 + p2g1 + p2p1g0;/ G0 = / p2 + / g2 / p1 + / g2 / gl / g0;Is written by That is, one P-type MOS transistor 106, a series circuit 3 in which two P-type MOS transistors 104 and 105 are connected in series, and three P-type M0S transistors 101, 102, and 103 are three. The / G0 is created by the series circuit 4 connected in series. In addition, one N-type MOS transistor 107, a series circuit 6 in which two N-type MOS transistors 108, 109 are connected in series, and three N-type M0S transistors 110, 111, and 112 are provided. The GO is created by the series circuit 7 connected in series.