Adder circuit and associated layout structure

摘要

In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations.; $PTEXTHILITALICPDATG/PDAT/ITALIC/HILHILBOLDPDAT0\=/PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT2\+/PDAT/BOLD/HILHILITALICPDATp/PDAT/ITALIC/HILHILBOLDPDAT2\·/PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT1\+/PDAT/BOLD/HILHILITALICPDATp/PDAT/ITALIC/HILHILBOLDPDAT2\·/PDAT/BOLD/HILHILITALICPDATp/PDAT/ITALIC/HILHILBOLDPDAT1\·/PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT0/PDAT/BOLD/HIL/PTEXT$ ; $PTEXTPDAT//PDATHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT0\=//PDAT/BOLD/HILHILITALICPDATp/PDAT/ITALIC/HILHILBOLDPDAT2\+//PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT2\·//PDAT/BOLD/HILHILITALICPDATp/PDAT/ITALIC/HILHILBOLDPDAT1\+//PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT2\·//PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT1\·//PDAT/BOLD/HILHILITALICPDATg/PDAT/ITALIC/HILHILBOLDPDAT0/PDAT/BOLD/HIL/PTEXT$ ;In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.