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Semiconductor memory device having two layers of bit lines arranged crossing with each other
Semiconductor memory device having two layers of bit lines arranged crossing with each other
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机译:具有两层彼此交叉布置的位线的半导体存储器件
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摘要
In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.
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