Semiconductor memory device, has word selecting signal lines and main word lines adjacent to plate poly and arranged on layer, and memory cell array connected between sub word lines and bit line pairs

摘要

The device has a memory cell array with a sub memory cell array connected between sub word lines and bit line pairs. Word selecting signal lines (PX1- PX4) and main word lines (NWL1- NWLi) adjacent to a plate poly (PP) are arranged on a layer. An electrode on the memory cell array is configured to apply a voltage for memory cells. The memory cell array transmits data between the bit line pairs and local data pairs.