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Dual Bandwidth Phase-Locked Loop Circuit

机译:双带宽锁相环电路

摘要

The present invention relates to a dual-bandwidth phase locked loop circuit, which is difficult to use in a communication system requiring fast switching because it takes more than a few tens of milliseconds to lock a frequency due to a narrow bandwidth in a conventional PLL. There was this.;Therefore, the present invention provides a wide bandwidth effect by reducing the locking time by flowing more current than the normal state in the charge pump operation to the desired voltage level quickly, and also reduces the current to a steady state when the charge pump is near There is an effect that enables precise control of the frequency by zooming.
机译:双带宽锁相环电路技术领域本发明涉及一种双带宽锁相环电路,由于在常规PLL中由于带宽较窄,锁定频率需要花费数十毫秒的时间,因此难以在需要快速切换的通信系统中使用。因此,本发明通过使比电荷泵操作中的正常状态更多的电流快速流到期望的电压水平,从而减少了锁定时间,从而提供了宽带宽的效果,并且当电流减小到稳态时,电荷泵就在附近。有一种效果可以通过缩放来精确控制频率。

著录项

  • 公开/公告号KR19990075838A

    专利类型

  • 公开/公告日1999-10-15

    原文格式PDF

  • 申请/专利权人 김영환;

    申请/专利号KR19980010289

  • 发明设计人 방대성;

    申请日1998-03-25

  • 分类号H03L7/00;

  • 国家 KR

  • 入库时间 2022-08-22 02:16:36

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