Semiconductor memory device having N-channel MOS transistor for pulling up PMOS sources of sense amplifiers

摘要

In a semiconductor memory device including a plurality of memory cells connected between sub word lines and bit lines, a plurality of sub word line driver columns for driving the sub word lines, and a plurality of sense amplifier columns for sensing voltages at the bit lines, a plurality of sense amplifier control circuits are provided at cross areas between the sub word line driver columns and the sense amplifier columns. A first sense amplifier control circuit is constructed by a CMOS circuit forming an interface between global input/output lines and local input/output lines. A second sense amplifier control circuit is constructed by an N-channel MOS circuit forming a pull down circuit for pulling down NMOS sources of flip-flops of the sense amplifier columns and a first pull up circuit for pulling up PMOS sources of the flip- flops of said sense amplifier columns. A third sense amplifier control circuit is constructed by a P-channel MOS circuit forming a second pull up circuit for pulling up the PMOS sources of the flip-flops of the sense amplifier columns.