首页> 外国专利> Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal

Equilibration circuit and method using a pulsed equilibrate signal and a level equilibrate signal

机译:使用脉冲平衡信号和电平平衡信号的平衡电路和方法

摘要

An exemplary 18 MBit memory array includes four banks of array blocks. At the end of an active cycle, the exemplary memory array is automatically taken back into precharge without waiting for a control signal. One edge of a clock causes the memory array to execute a useful cycle, then to automatically reset itself in preparation for a new cycle, preferably using two sets of precharge signals- one is an automatically timed pulse, while the other stays on until the start of the next cycle. Both turn on automatically at the same time just after the selected word line is brought low. One equilibrate signal is turned off by a timed pulse just when the bit line equilibration is substantially complete (i. e., at the end of the active cycle), while the other equilibrate signal is turned off by the start of the subsequent cycle. The pulsed equilibrate signal drives much larger internal capacitive loads, such as large equilibration devices, while the non-pulsed (i.e., "level") equilibrate signal drives fewer and/or much smaller devices which somewhat assist the larger pulsed equilibrate devices in equilibrating the various nodes, but which fewer and/or much smaller devices alone maintain the equilibration until the next active cycle. The total capacitance of the various equilibration signal lines which must be discharged as an immediate result of the start of a new cycle is greatly reduced and the buffering to drive this reduced capacitance can be accomplished with fewer progressively larger buffering stages. Therefore, the equilibration is turned off with less delay after the initiating control signal, reducing the access time of the memory array.
机译:示例性的18MBit存储器阵列包括四组阵列块。在活动周期结束时,示例性存储阵列将自动恢复为预充电状态,而无需等待控制信号。时钟的一个边沿使存储阵列执行一个有用的周期,然后自动重置自身以准备新的周期,最好使用两组预充电信号-一组是自动定时脉冲,而另一组则保持开启状态直到开始下一个周期。所选字线变低后,两者都会同时自动自动打开。恰在位线平衡基本完成时(即,在有效周期的末尾),一个定时信号将一个平衡信号关闭,而另一平衡信号则在随后的周期开始时关闭。脉冲平衡信号驱动较大的内部电容负载,例如大型平衡设备,而非脉冲(即“电平”)平衡信号驱动较少和/或较小的设备,这在一定程度上有助于较大的脉冲平衡设备平衡负载。各个节点,但只有较少和/或较小的设备才能保持平衡,直到下一个活动周期为止。作为新循环开始的直接结果,必须放电的各种平衡信号线的总电容大大降低了,并且用较少的逐渐增大的缓冲级就可以完成驱动该减小的电容的缓冲。因此,在启动控制信号后,均衡会以较小的延迟关闭,从而减少了存储阵列的访问时间。

著录项

  • 公开/公告号US6104653A

    专利类型

  • 公开/公告日2000-08-15

    原文格式PDF

  • 申请/专利权人 INTEGRATED DEVICE TECHNOLOGY INC.;

    申请/专利号US19990451042

  • 发明设计人 ROBERT J. PROEBSTING;

    申请日1999-11-30

  • 分类号G11C7/00;

  • 国家 US

  • 入库时间 2022-08-22 01:36:25

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号