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DEFECT ANALYZING METHOD IN SEMICONDUCTOR PRODUCT MANUFACTURING PROCESS

机译:半导体产品制造过程中的缺陷分析方法

摘要

PROBLEM TO BE SOLVED: To provide a defect analyzing method in a semiconductor product manufacturing process in which intrinsic defects are detected on the basis of transfer of defects generated in each process to the following processes, and analysis of yield information corresponding to a process and prediction of yield in the course of a process are enabled.;SOLUTION: The intrinsic defects turning to a cause of imperfect operation are detected and counted to plural function blocks formed in plural chips on a wafer. With respect to the counted intrinsic defects, failure judgment is performed to a function element of the function block in such a manner that Block 0 to Block 2 set a count value 1 as failure judgment reference and Block 3 to Block 6 set a count value 10 as failure judgment reference. On the basis of the judged result, the ratio of the number of imperfect chips to the total number of chips of a wafer is calculated as a killer rate. Final prediction of yield on the basis of relationship between yield of a production line and the killer rate, adjustment of the final prediction yield by the control of the killer rate, and improvement of the final prediction yield by level control of the killer rate in the course of a process are enabled.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种半导体产品制造过程中的缺陷分析方法,其中根据在每个过程中产生的缺陷向以下过程的转移来检测固有缺陷,并分析与过程和预测相对应的良率信息解决方案:解决方案:检测到导致不完美操作的内在缺陷,并将其计入晶圆上多个芯片中形成的多个功能块。对于计数的固有缺陷,以块0至块2将计数值1设置为故障判断基准并且块3至块6设置计数值10的方式对功能块的功能元件执行故障判断。作为故障判断参考。根据判断结果,计算出不合格芯片数与晶片芯片总数之比作为杀灭率。根据生产线的产量与杀灭率之间的关系,对最终产量进行预测,通过控制杀灭率来调整最终预测产量,并通过控制杀灭率的水平来提高最终预测产量。进程的过程已启用。;版权:(C)2002,JPO

著录项

  • 公开/公告号JP2002151561A

    专利类型

  • 公开/公告日2002-05-24

    原文格式PDF

  • 申请/专利权人 SONY CORP;

    申请/专利号JP20000347009

  • 发明设计人 TANAKA TORU;

    申请日2000-11-14

  • 分类号H01L21/66;H01L21/02;

  • 国家 JP

  • 入库时间 2022-08-22 00:56:25

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