Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor. ;The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
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