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Recovery mechanism for L1 data cache parity errors
Recovery mechanism for L1 data cache parity errors
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机译:L1数据高速缓存奇偶校验错误的恢复机制
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摘要
A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.
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