ENHANCED SINGLE EVENT UPSET IMMUNE LATCH CIRCUIT

摘要

A single event upset (SEU) immune latch is described comprising first PMOS and NMOS transistors coupled together at their input; first isolation PMOS and NMOS transistors coupled together and in parallel between the outputs of said first PMOS and NMOS transistors and whose gates are connected to ground and VDD, respectively; second PMOS and NMOS transistors receiving at their gates the outputs of said first PMOS and NMOS transistors and being connected at their inputs to VDD and ground, respectively; second isolation PMOS and NMOS transistors coupled together and in parallel between the outputs of said second PMOS and NMOS transistors and whose gates are connected to ground and VDD, respectively; third PMOS and NMOS transistors receiving at their gates the outputs of said second PMOS and NMOS transistors and being connected at their inputs to VDD and ground, respectively; a feedback PMOS transistor coupled between the outputs of said first and said third PMOS transistors; a feedback NMOS transistor coupled between the outputs of said first and said third NMOS transistors; a data input coupled to the input of said first PMOS and NMOS transistors; a clock signal coupled to the gates of the first NMOS transistor and the feedback PMOS transistor; and a complementary clock signal coupled to the gates of the first PMOS transistor and the feedback NMOS transistor.