首页> 外国专利> Non-volatile memory device, e.g. electrically-erasable programmable read only memory cell, comprises gate insulating films, tunnel insulating film, memory transistor gate, select transistor gate, and three doped regions

Non-volatile memory device, e.g. electrically-erasable programmable read only memory cell, comprises gate insulating films, tunnel insulating film, memory transistor gate, select transistor gate, and three doped regions

机译:非易失性存储设备,例如电可擦可编程只读存储单元,包括栅极绝缘膜,隧道绝缘膜,存储晶体管栅极,选择晶体管栅极和三个掺杂区

摘要

A non-volatile memory device has gate insulating films formed on a semiconductor substrate. A tunnel insulating film is interposed between the adjacent gate insulating films. A memory transistor gate is formed on tunnel and gate insulating films. A select transistor gate is formed on gate insulating film spaced from memory transistor gate. Three doped regions are formed on the substrate. A non-volatile memory device, e.g. electrically-erasable programmable read only memory (EEPROM) cell, consists of gate insulating films, tunnel insulating film (412), memory transistor gate (450), select transistor gate (460), and three doped regions. The gate insulating films are formed on a semiconductor substrate and spaced apart from each other. The tunnel insulating film is interposed between the adjacent gate insulating films. The memory transistor gate is formed on the tunnel and gate insulating films interposing the tunnel insulating film between them. The select transistor gate is formed on the gate insulating film spaced apart from the memory transistor gate. The first doped region is formed in substrate portion under the memory transistor gate and overlaps one end of the select transistor gate. The second doped region is formed in substrate portion spaced apart from the first doped region and overlaps one end of memory transistor opposite to the select transistor gate. The third doped region is formed in substrate portion spaced apart from the first doped region and overlaps the other end of the select transistor gate. The second doped region is shallower in depth than the first and third doped regions, and includes low-density and high-density doped regions. An INDEPENDENT CLAIM is included for fabrication of non-volatile memory device.
机译:非易失性存储装置具有在半导体基板上形成的栅极绝缘膜。隧道绝缘膜介于相邻的栅极绝缘膜之间。在隧道和栅极绝缘膜上形成存储晶体管栅极。选择晶体管栅极形成在与存储晶体管栅极隔开的栅极绝缘膜上。在衬底上形成三个掺杂区。非易失性存储设备,例如电可擦可编程只读存储器(EEPROM)单元,由栅极绝缘膜,隧道绝缘膜(412),存储器晶体管栅极(450),选择晶体管栅极(460)和三个掺杂区组成。栅绝缘膜形成在半导体衬底上并且彼此间隔开。隧道绝缘膜介于相邻的栅极绝缘膜之间。在隧道上形成存储晶体管栅极,并且在其之间插入隧道绝缘膜的栅极绝缘膜。选择晶体管栅极形成在与存储晶体管栅极间隔开的栅极绝缘膜上。第一掺杂区形成在存储晶体管栅极下方的衬底部分中,并且与选择晶体管栅极的一端重叠。第二掺杂区形成在与第一掺杂区间隔开的衬底部分中,并且与存储晶体管的与选择晶体管栅极相对的一端重叠。第三掺杂区形成在与第一掺杂区间隔开的衬底部分中,并且与选择晶体管栅极的另一端重叠。第二掺杂区的深度比第一和第三掺杂区的深度浅,并且包括低密度和高密度掺杂区。包括独立权利要求,用于制造非易失性存储器件。

著录项

  • 公开/公告号DE10206057A1

    专利类型

  • 公开/公告日2002-08-14

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号DE2002106057

  • 发明设计人 PARK WEON-HO;

    申请日2002-02-07

  • 分类号H01L27/115;H01L21/8247;

  • 国家 DE

  • 入库时间 2022-08-22 00:26:46

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