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Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell
Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell
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机译:具有用于通过使用冗余存储单元进行维修分析的自测试电路的半导体集成电路装置
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摘要
A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.
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