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non-volatile semiconductor memory devices having sector structure formed with common bulk

机译:具有形成有共同体的扇区结构的非易失性半导体存储器件

摘要

PURPOSE: A non-volatile semiconductor memory device having a sector structure formed with a shared bulk is provided to minimize or reduce a layout area by sharing a bulk region. CONSTITUTION: A cell array block(101) is formed with a plurality of cell transistors. A column decoder block(103) is connected with the cell array block(101) in order to perform a column decoding process. A plurality of word lines(WL0 to WLn-1) and a plurality of bit lines(BL0 to BLm-1) are formed in the cell array block(101). Gates of cells of n number are commonly connected with one word line. Drains of cells of m number are commonly connected with one bit line. The bit lines(BL0 to BLm-1) of m number are connected with a common data line through a corresponding column decoder. The common data lines of I number are connected with write drivers(200,210) and sense amplifiers(300,310). Bulk terminals of memory cell transistors and bulk terminals of transistors(T1,T2,T3) for forming the column decoder block(103) are commonly connected with a bulk driver(400). All source terminals of the memory cell transistors are connected with the same source line(SL) and driven by a source line driver(500).
机译:目的:提供一种具有形成有共享块的扇区结构的非易失性半导体存储器件,以通过共享块区来最小化或减小布局面积。构成:一个单元阵列块(101)由多个单元晶体管形成。列解码器块(103)与单元阵列块(101)连接,以便执行列解码处理。在单元阵列块(101)中形成多条字线(WL0至WLn-1)和多条位线(BL0至BLm-1)。 n个单元的栅极通常与一条字线连接。通常,m个单元的漏极与一位线连接。 m个位线(BL0至BLm-1)通过相应的列解码器与公共数据线连接。 I号公共数据线与写驱动器(200,210)和读出放大器(300,310)连接。用于形成列解码器块(103)的存储单元晶体管的体端子和晶体管(T1,T2,T3)的体端子通常与体驱动器(400)连接。存储单元晶体管的所有源极端子都与相同的源极线(SL)连接并且由源极线驱动器(500)驱动。

著录项

  • 公开/公告号KR20020089587A

    专利类型

  • 公开/公告日2002-11-30

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20010028257

  • 发明设计人 LEE BYEONG HUN;LEE SEUNG GEUN;

    申请日2001-05-23

  • 分类号G11C16/06;

  • 国家 KR

  • 入库时间 2022-08-21 23:48:32

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