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Semiconductor device having a doped lattice matching layer and a method of manufacture therefor

机译:具有掺杂晶格匹配层的半导体器件及其制造方法

摘要

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.
机译:本发明提供一种半导体器件,其制造方法以及包括该半导体器件的集成电路。半导体器件可以包括位于掺杂衬底上方的掺杂掩埋层和位于掺杂掩埋层上方的掺杂外延层。半导体器件可以进一步包括位于衬底和掩埋层之间的第一掺杂晶格匹配层和位于掺杂掩埋层和掺杂外延层之间的第二掺杂晶格匹配层。

著录项

  • 公开/公告号US6855991B2

    专利类型

  • 公开/公告日2005-02-15

    原文格式PDF

  • 申请/专利权人 WEN LIN;CHARLES W. PEARCE;

    申请/专利号US20040814680

  • 发明设计人 CHARLES W. PEARCE;WEN LIN;

    申请日2004-03-31

  • 分类号H01L31/119;

  • 国家 US

  • 入库时间 2022-08-21 22:20:12

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