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A non-volatile memory device supporting high-parallelism test at wafer level
A non-volatile memory device supporting high-parallelism test at wafer level
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机译:一种支持晶圆级高并行度测试的非易失性存储设备
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摘要
A non-volatile memory device (100) is proposed. The non-volatile memory device includes a chip (105) of semiconductor material. The chip includes a memory (202) and control means (204,210,214) for performing a programming operation (314), an erasing operation (312) and a reading operation (316) on the memory in response to corresponding external commands. The chip further includes testing means (118, 120, 220, 225, 230) for performing at least one test process including the repetition of at least one of said operations by the control means, and a single access element (118) for enabling the testing means.
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