Algorithm pattern generator for memory tester, includes address and data generator for generating address and data logic for memory device test via address and data scrambling with respect to each cycle

摘要

An address generator generates an address logic for memory device test via address scrambling with respect to each cycle provided by the clock signal generating phase locked loop (PLL). A data generator generates a data logic for the test via data scrambling with respect to each cycle. A data comparator compares data generated in the data generator and a test data for each of the cycles and stores failed memory data. Independent claims are also included for the following: (1) memory tester; (2) memory testing method; and (3) computer-readable medium storing memory testing program.