Single event upset tolerant memory cell layout

摘要

Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.