首页> 外国专利> SEPARATE TESTING OF CONTINUITY BETWEEN AN INTERNAL TERMINAL IN EACH CHIP AND AN EXTERNAL TERMINAL IN A STACKED SEMICONDUCTOR DEVICE

SEPARATE TESTING OF CONTINUITY BETWEEN AN INTERNAL TERMINAL IN EACH CHIP AND AN EXTERNAL TERMINAL IN A STACKED SEMICONDUCTOR DEVICE

机译:堆叠半导体器件中每个芯片的内部端子和外部端子之间的导通性分别测试

摘要

A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal.
机译:公开了一种堆叠半导体器件,其能够基于每个芯片的内部端子进行测试以确定每个芯片中的外部端子和对应的内部端子之间是否存在导通性。该半导体器件包括用于每个芯片的连续性测试专用端子,以及分别连接在每个芯片中的内部端子和与该芯片相关联的连续性测试专用端子之间的连续性测试元件。在与要检查其连接状态的内部端子相关联的外部端子与与包括该内部端子的芯片相关联的连续性测试专用端子之间施加电压,以使得与内部端子相关联的连续性测试元件导电。此后,测量流过连续性测试元件的电流值,以确定内部端子的连接状态。

著录项

  • 公开/公告号US2009153177A1

    专利类型

  • 公开/公告日2009-06-18

    原文格式PDF

  • 申请/专利权人 KAYOKO SHIBATA;

    申请/专利号US20080328129

  • 发明设计人 KAYOKO SHIBATA;

    申请日2008-12-04

  • 分类号G01R31/26;H01L23/52;

  • 国家 US

  • 入库时间 2022-08-21 19:36:31

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号