METHOD AND DEVICE FOR IMPROVING THE STABILITY OF 6T SGT CMOS SRAM CELL

摘要

Provided are a device configuration of a 6T SGT CMOS SRAM cell having a sufficiently high SNM, and a method for manufacturing the device configuration. The SGT device configuration comprises an access NMOS device having a side wall face formed into a first crystal plane so as to acquire a first carrier mobility, a pull-down NMOS device having a side wall face formed into a second crystal plane so as to acquire a second carrier mobility, and a pull-up PMOS device having a side wall face formed into a third crystal plane so as to acquire a third carrier mobility. At least one of the first, second or third crystal planes is different from the remaining two crystal planes. The different crystal plane is formed of an SGT transistor having a plane of a low carrier mobility and a relatively low gain, and an SGT transistor having a plane of a high carrier mobility and a relatively high gain. The SGT having the plane of the high mobility has a higher gain than that of the SGT having the plane of the low mobility.