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SINGLE ELECTRON TRANSISTOR WITH VERTICAL QUANTUM DOT AND FABRICATION METHOD OF THE SAME

机译:垂直量子点的单电子晶体管及其制造方法

摘要

A single electron transistor having a vertical quantum dot and a manufacturing method thereof are provided to integrate simultaneously a MOSFET of a vertical channel structure by forming a quantum dot at a vertical channel. A single electron transistor having a vertical quantum dot includes a silicon layer(10), a first gate insulating layer(22), a control gate(56), a second gate insulating layer(70), and a first and second sidewall gates(82). The silicon layer of constant width and height is patterned in a longitudinal direction on an upper part of a buried oxide layer(2) of a SOI substrate. The first gate insulating layer is formed on a vertical side of the silicon layer. The control gate is formed at both sides of the first gate insulating layer on the buried oxide layer. The control gate is adjacent to the silicon layer. The second gate insulating layer is formed to surround three surfaces of the control gate. The first and second sidewall gates come in contact with the second insulating layer at both sides of the first gate insulating layer. The first and second sidewall gates are formed on the buried oxide layer at both sides of the control gate.
机译:提供具有垂直量子点的单电子晶体管及其制造方法,以通过在垂直沟道处形成量子点而同时集成垂直沟道结构的MOSFET。具有垂直量子点的单电子晶体管包括硅层(10),第一栅极绝缘层(22),控制栅极(56),第二栅极绝缘层(70)以及第一和第二侧壁栅极( 82)。在SOI衬底的掩埋氧化物层(2)的上部在纵向上图案化具有恒定宽度和高度的硅层。第一栅极绝缘层形成在硅层的垂直侧上。控制栅极形成在掩埋氧化物层上的第一栅极绝缘层的两侧。控制栅极与硅层相邻。第二栅极绝缘层形成为围绕控制栅极的三个表面。第一侧壁栅极和第二侧壁栅极在第一栅极绝缘层的两侧与第二绝缘层接触。第一侧壁栅极和第二侧壁栅极形成在控制栅极两侧的掩埋氧化物层上。

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