scan test design method, scan test circuit, scan testschaltungseinfu00fcge cad program, highly integrated circuit and mobile digital device

摘要

PROBLEM TO BE SOLVED: To suppress the power consumption by considerably reducing the number of delay elements to be inserted to data lines of shift registers in order to secure a hold time in the shift operation of a scan shift register in scan test circuit design.;SOLUTION: A plurality of flip flop circuits (circuits 102a, circuits 102b, circuits 102c, etc.) driven by elements 101f of the last stages are mutually connected in series to constitute a subscan chain in terms of element 101f of the last stage of a clock tree T. Subscan chains between which the difference in the number of delay elements from a clock supply point S of the clock tree T is minimum (that is, the difference is one stage) are mutually connected. Further, subscan chains are mutually connected so that data is shifted from flip flop circuits of long clock delay to flip flop circuits of short clock delay.;COPYRIGHT: (C)2005,JPO&NCIPI