SCAN TEST DESIGN METHOD, SCAN TEST CIRCUIT, SCAN TEST CIRCUIT INSERTION CAD PROGRAM, LARGE-SCALE INTEGRATED CIRCUIT, AND MOBILE DIGITAL DEVICE

摘要

In scan test circuit design, a plurality of flipflop circuits (102a, 102b or 102c) driven with each of final-stage elements 101f of a clock tree T are connected in series, to form a sub-scan chain. Also, sub-scan chains smallest in the relative difference in the number of stages of delay elements existing from the clock supply point S of the clock tree T (i.e., sub-scan chains different by one stage) are connected to each other. Further, sub-scan chains are connected so that data shift be made from a flipflop circuit larger in clock delay to a flipflop circuit smaller in clock delay. This reduces the number of delay elements inserted in data lines of a shift register for hold time guarantee in shift operation of the scan shift register, and suppresses power consumption.