Design for Testability of Digital Circuit for in System Programmable Logic Device Based on Level Sensitive Scan Design

摘要

To improve the measurable degree of digital circuit of ISPLD (In System Programmable Logic Device) and to solve the self-test problem of the circuit, design for testability is used. Aimed at the characters of ISPLD's structure and function, level sensitive design and scan channel design are adopted, and it uses polarity stability trigger to build the level sensitive scan channel, and realizes the structural design for testability of the circuit. Used the software of ispDesignEXPERT system to realize the design in the device of ispLSI1016.