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Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors
Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors
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机译:使用双栅晶体管改善SRAM设计中的读/写裕量
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摘要
An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.
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