机译:紧凑型低VDDmin 6T SRAM,采用双分裂控制辅助方案,提高了单元稳定性,读取速度和写入余量
National Tsing Hua University, Hsinchu, Taiwan;
National Tsing Hua University, Hsinchu, Taiwan;
United Microelectronics Corporation, Hsinchu, Taiwan;
United Microelectronics Corporation, Hsinchu, Taiwan;
United Microelectronics Corporation, Hsinchu, Taiwan;
National Tsing Hua University, Hsinchu, Taiwan;
Fukuoka Institute of Technology, Fukuoka, Japan;
SRAM cells; Layout; Circuit stability; MOS devices; Transistors; Stability criteria;
机译:基于电荷等离子体DLTFET的6T SRAM单元的读写稳定性评估
机译:内部写回和写前读取方案消除了对SRAM中半选单元的干扰
机译:有机和混合6-T SRAM单元的噪声容限,写入能力和读取稳定性的设计和分析
机译:CMOS 6T SRAM阵列的全数字读取稳定性和写入裕量表征方案
机译:基于7NM FinFET的6T SRAM细胞瞬态和DC分析性能分析
机译:增强步态稳定性的步骤:步幅频率步幅长度和步行速度对局部动态稳定性和稳定性裕度的影响
机译:用于低功耗的恢复电路减少6T和8T SRAM单元的摆动,改进了读写边距