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Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit
Memory Cell Arrangement and Method for Reading State Information From a Memory Cell Bypassing an Error Detection Circuit
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机译:存储器单元布置和用于通过错误检测电路从存储器单元读取状态信息的方法
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摘要
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, at least one error detection circuit, and a controller configured to control a read operation to read state information from the at least one memory cell by reading a memory cell state information bypassing the at least one error correction circuit, or by reading the memory cell state information and supplying it to the at least one error correction circuit.
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