WAFER LEVEL CHIP SIZE PACKAGE AND A MANUFACTURING METHOD THEREOF, CAPABLE OF ALLEVIATING THE STRESS GENERATED IN A SOLDER BALL WHICH IS FORMED ON A SEMICONDUCTOR CHIP

摘要

PURPOSE: A wafer level chip size package and a manufacturing method thereof are provided to alleviating the stress concentration applied to a solder ball due to the difference between coefficients of thermal expansion of a resin sealing unit and the solder ball by forming a stress relaxation unit having a coefficient of thermal expansion lower than the resin sealing unit.;CONSTITUTION: A wafer level chip size package(30) includes a semiconductor chip, the first insulation layer, a re-wiring layer, the first solder ball, a stress relaxation unit, and a resin sealing unit. On the semiconductor chip, a bonding pad is formed. The first insulation layer is formed in an upper side of the semiconductor chip excepting for the bonding pad. One end of the re-wring layer is connected to a bonding pad on the first insulation layer and the other end has a connection pad. The first solder ball(39) is formed in the connection pad. The stress relaxation unit is formed as surrounding the outer side of the first solder ball. The resin sealing unit(40) is formed to seal the re-wiring layer, the first insulation layer and the first solder ball.;COPYRIGHT KIPO 2010